Circuit boards provide a substantially planar surface on which electronic components can be mounted. Circuit paths for the components are provided by forming conductive lines on the circuit board that connect component-mounting through-holes in the board. Electrical leads that extend from the components are electrically connected to the conductive lines when the components are mounted to the board through-holes. Circuit boards can be single-sided, in which case components are mounted only on one surface of the circuit board, or circuit boards can be double-sided, in which case components can be mounted to both surfaces of the board. Generally, a single-sided board comprises a non-conductive substrate, such as a glass fiber-resin combination, with conductive lines formed on the board surface opposite the component mounting surface. A double-sided board typically comprises a central conductive layer clad on top and bottom surfaces with non-conductive separation layers, with conductive lines formed on one or both board surfaces.
Printed circuit boards are generally manufactured using either a subtractive etch process, an acid plate pattern plating process, or an electroless pattern plating process. The electroless plating process is also referred to as additive pattern plating. In all of these processes, a circuit mask that lays out the desired pattern of the conductive lines is transferred to the circuit board by printing the circuit mask pattern onto a polymeric radiation-sensitive resist material deposited on the board. The resist material is irradiated in the pattern of the circuit mask so that it is physically transformed where it is irradiated and is unchanged where shielded by the circuit mask. The resist material thereafter can be developed by exposing it to a fast-reacting chemical solution that selectively removes either the irradiated material (called a positive-tone resist) or removes the non-irradiated material (negative-tone resist).
The subtractive etch process typically begins with a board substrate comprised of a non-conductive material on which a layer of conductive material such as a metal is plated. One such metal which can be used as this conductive material is copper. A layer of resist material is then deposited and developed in the circuit mask pattern so as to expose the conductive material where circuit paths are not desired. The exposed conductive material in the resist voids is then etched away. Finally, the remaining resist material is removed, leaving behind conductive lines wherever circuit paths were desired.
The subtractive etch process provides good control over circuit path height because the amount of conductive material plated onto the substrate generally can be controlled rather well. Precisely controlled circuit path height is especially important with surface mount techniques. Unfortunately, the subtractive etch process does not provide precise control over circuit path width, due to plating variation and lack of sharply defined path edges. The lack of width control is disadvantageous with current demands for increasingly high component mounting densities that require relatively thin conductive lines placed in close proximity to each other.
The acid plate pattern plating process uses electroplating techniques to deposit conductive lines in circuit paths defined by resist material voids. That is, conductive foil layer on the circuit board is connected to an electrode and the conductive material is deposited onto the board in the resist material voids using an oppositely charged electrode. The width of the conductive lines is generally dependent on the developed resist pattern, which typically is of photographic sharpness. Pattern plating thereby provides good control over circuit path width and permits conductive lines of relatively fine width. The circuit path height, however, can vary greatly depending on the density of the desired conductive lines. In particular, isolated conductive lines are thicker than densely packed conductive lines. Thus, line height is not precisely controlled by the acid plate process. The additive plate process is similar to the acid plate process, except that chemical plating techniques are used rather than electro-plating techniques. Additive plate fabrication generally requires more time to complete as compared to acid plate fabrication but is not as susceptible to circuit path height variation according to line density. Height variations for additive plate fabrication, however, experiences height variation from side to side differences as well as copper module formation.
As stated above there are several different methods of plating and creating printed circuit lines on substrates such as circuit boards and circuit cards which are presently in use. Of these, additive panel plating is utilized to control both line height and line width. However, this method is costly and time-consuming. The above disclosed related application describes a method of producing fine-line circuit boards using chemical polishing. As disclosed therein, the printed circuit board is produced from an initial substrate board coated with a resist layer. The resist layer is patterned according to a circuit mask that defines circuit paths. The pattern resist layer is then selectively removed from the board in the desired circuit paths, and a conductive material is deposited on the board in the areas where the resist was removed as defined by the circuit mask. The conductive material is deposited so that the height of the conductive material relative to the substrate board equals or exceeds the height of the resist layer relative to the substrate board. In a first etching step, a low reactive solution is applied over the conductive material and slowly dissolves it by first forming a film layer. Mechanical contact is then used to remove this film layer on any surface above the resist layer. The removal of the thin film layer allows a new conductive material surface layer to be exposed to the solution, and a new film layer to be formed. This process continues until the height of the resist layer is reached. At this point, when contact with the conductive material cannot be made without contacting the resist layer, a final film layer is formed. This final film layer then becomes a barrier to the low reactive solution and, in fact, on any area that is below the resist layer, such as a plated through hole. In this way, no abrasive materials are used in ensuring that the height of the conduct line will be substantially uniform and will conform to substrate undulations and surface irregularities. Conductive line width control is defined by the developed resist image. Circuit boards are then produced so as to have uniform height and precise width, even with organic flexible composition substrates. The etching solution is applied, allowed to react and form a barrier, then removed. Then, a new solution is applied, the barrier is formed, and the barrier is removed. This process is repeated until an essentially planarized surface of copper circuitry is obtained. Also, if the surface of the product is relatively regular and uniform, the card may be inspected using an automatic optical inspection ("AOI") system. Due to surface irregularities inherent to this process, however, AOI systems cannot be used. This results in high scrap and defective product. These irregularities on the metal surface features are typically caused by either the pattern plate itself or the post-process operations. Furthermore, these irregularities produce an excessive number of re-calls or product that is untestable by the AOI system.
While this technique is quite effective in producing a good planarized surface, nevertheless, it is essentially a batch process, as opposed to a continuous process, and requires iterative repetition of the forming and removing of the barrier and checking the height. This is time-consuming and requires significant manual operator involvement with significant operator judgment involved. Thus, while this process is effective, it is somewhat slow, especially if a large reduction in height of the circuit lines is required. Furthermore, the surface irregularities resulting from this process prevent automatic optical inspection of the resulting product. Therefore it is an object of the present invention to provide an improved process for planarizing metal surfaces on a substrate material.